IDT82V3202NLG【PDF 28/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Functional Description

September 11, 2009

FUNCTIONAL DESCRIPTION

3.1

RESET

The reset operation resets all registers and state machines to their

default value or status.

After power on, the device must be reset for normal operation.

For a complete reset, the RST pin must be asserted low for at least

50 s. After the RST pin is pulled high, the device will still be in reset

state for 500 ms (typical). If the RST pin is held low continuously, the

device remains in reset state.

3.2

MASTER CLOCK

A nominal 12.8000 MHz clock, provided by a crystal oscillator, is

input on the OSCI pin. This clock is provided for the device as a master

clock. The master clock is used as a reference clock for all the internal

circuits. A better active edge of the master clock is selected by the

OSC_EDGE bit to improve jitter and wander performance.

In fact, an offset from the nominal frequency may input on the OSCI

pin.

This

offset

can

compensated

setting

the

NOMINAL_FREQ_VALUE[23:0] bits. The calibration range is within

±741 ppm.

The performance of the master clock should meet GR-1244-CORE,

GR-253-CORE, ITU-T G.812 and G.813 criteria.

Table 2: Related Bit / Register in Chapter 3.2

Bit

Register

Address (Hex)

NOMINAL_FREQ_VALUE[23:0]

NOMINAL_FREQ[23:16]_CNFG, NOMINAL_FREQ[15:8]_CNFG, NOMINAL_FREQ[7:0]_CNFG

06, 05, 04

OSC_EDGE

DIFFERENTIAL_IN_OUT_OSCI_CNFG

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